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19-2607; Rev 0; 10/02
MAX3953 Evaluation Kit
General Description
The MAX3953 evaluation kit (EV kit) is an assembled surface-mount demonstration board that provides easy evaluation of the MAX3953 10Gbps 1:16 deserializer with clock data recovery (CDR). The EV kit includes all components necessary to interface with +3.3V CML inputs and LVDS outputs. o Single +3.3V Supply o 9.953Gbps/10.312Gbps Evaluation o Fully Assembled and Tested o Fully Matched with High-Bandwidth SMP Connectors at the Input
Features
Evaluates: MAX3953
Component List
DESIGNATION QTY C1 C2, C4, C16 C3, C5, C7 C6, C10 C8 C9 C13, C15 J1, J2, J7-J40 J3, J4 J41, J42 J43, J44 JU2 L1 R1 R5-R16, R18-R22 TP1, TP2 U1* None None* None* None* 1 3 3 2 1 1 2 36 2 2 2 1 1 1 17 2 1 4 1 1 1 DESCRIPTION 2.2F 10% ceramic capacitor (0805) 0.1F 10% ceramic capacitors (0402) 0.01F 10% ceramic capacitors (0402) 0.1F 10% ceramic capacitors (0201) 33F 10% tantalum capacitor, case B 0.047F 10% ceramic capacitor (0402) 0.01F 10% ceramic capacitors (0201) SMB connectors SMP698 connectors, edge mount Test points Do not install 10 x 2 pin headers, 0.1in centers 56nH 10% inductor (0805) 0805HS-560TKBC 100 1% resistor (0402) Open Test points MAX3953UGK 68-pin QFN Shunts MAX3953 EV kit circuit board MAX3953 EV kit data sheet MAX3953 data sheet AVX Coilcraft Murata SUPPLIER PART MAX3953EVKIT
Ordering Information
TEMP RANGE 0oC to +85oC IC PACKAGE 68 QFN
Component Suppliers
PHONE 843-448-9411 408-224-8566 770-436-1300 FAX 843-448-1943 408-224-6304 770-436-3030
*Supplied by Maxim
________________________________________________________________ Maxim Integrated Products
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For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
MAX3953 Evaluation Kit Evaluates: MAX3953
Quick Start
1) Apply +3.3V to the VCC (J41) pin. Connect powersupply ground to GND (J42). Set the supply current limit to 500mA. 2) Install shunts from pins 1 to 2, 7 to 8, 9 to 10, and 17 to 18, of JU2. 3) Apply a differential input clock from 200mVP-P to 1600mVP-P at 622.08MHz to J1 and J2 (REFCLK+ and REFCLK-). 4) Apply a differential input signal from 100mVP-P to 1600mV P-P at 9.95328Gbps to J3 and J4 (SDI+ and SDI-). 5) Use a 50 terminated oscilloscope to monitor the output data on any of the parallel output lines (PDO0 to PDO15). Monitor the output clock on PCLKO+ and PCLKO-. The oscilloscope should show a 622.08MHz clock output and a 622.08Mbps data output. LVDS outputs must be AC-coupled into the oscilloscope.
JU2 19 SYNC_ERR CLKSEL GND VCC GND REFSET VCC GND RATESET VCC 3 LOS_IN 1 VCC GND
Detailed Description
The MAX3953 EV kit simplifies evaluation of the MAX3953 1:16 deserializer with CDR. The EV kit operates from a single +3.3V supply and includes all the external components necessary to interface with +3.3V CML inputs and LVDS outputs. Transmission-line test structures (J43 to J44) are included on the evaluation board to allow measurement of signal loss and dispersion of clock and data signals at 10GHz.
Figure 1. JU2 Header Configuration
Applications Information
Connecting LVDS Outputs to 50 Oscilloscope Inputs
To monitor LVDS signals with 50 oscilloscope inputs, set the inputs of the oscilloscope to "AC-coupling" or place a DC block in series with each output. If you are observing only one output with a 50 probe, balance the complementary output with a DC block and a 50 terminator to ground.
R5-R16 and R18-R22. Note that this does not provide as good a termination scheme as using the 50 inputs on an oscilloscope, which degrades the resulting output.
Exposed-Pad Package
The 68-pin QFN package with exposed pad incorporates features that provide a very low thermal-resistance path for heat removal from the IC, either to a PC board or to an external heatsink. The exposed pad on the MAX3953 must be soldered directly to a ground plane with good thermal conductance. The 10 x 2 header (JU2) provides control for the input configuration of the MAX3953. Figure 1 shows the control structure for the JU2 header.
Connecting LVDS Outputs to HighImpedance Oscilloscope Inputs
To monitor LVDS signals with high-impedance oscilloscope inputs, install 100 (0402) resistors on locations
Configuration for JU2
2
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MAX3953 Evaluation Kit
Clock Holdover
The clock holdover mode of the MAX3953 is designed to provide an accurate parallel clock in the event of a loss-of-lock (LOL) or loss-of-signal (LOS) condition. The activation of the holdover mode is controlled by the SYNC_ERR, LOS_IN, and CLKSEL pins. CLKSEL is an input signal used to select the VCO to lock on to incoming data (SDI) or the reference clock (REFCLK). Connecting SYNC_ERR to CLKSEL (pin 17 to 18 on JU2) activates the holdover mode.
Evaluates: MAX3953
Adjustment and Control Description (see Quick Start first)
COMPONENT JU2 NAME CLKSEL FUNCTION Output Clock Selector, TTL. CLKSEL is the control input for clock holdover. When CLKSEL = GND, PCLKO is derived from the input data. When CLKSEL = VCC, PCLKO is derived from the reference clock. Reference Clock Select Input, TTL. When the reference clock is 155MHz/161MHz, set REFSET to GND. When the reference clock is 622MHz/644MHz then set REFSET to VCC. Serial Data Rate Select Input, TTL. When the input serial data stream is 9.953Gbps, set RATESET to GND. When the input serial data stream is 10.312Gbps, set RATESET to VCC. Loss-of-Signal Input, TTL. The LOS_IN is an external input. Clock holdover is activated when LOS_IN is TTL low. (See the Clock Holdover section.) Synchronization Error Output, TTL. SYNC_ERR is intended to drive CLKSEL for holdover mode. (See the Clock Holdover section.) Loss-of-Lock Indicator Output, TTL. LOL signals a TTL low when the VCO frequency is more than 1000ppm from the reference clock frequency. LOL signals a TTL high when the VCO frequency is within 500ppm of the reference clock frequency. (See the Clock Holdover section.)
JU2 JU2 JU2 TP1
REFSET RATESET LOS_IN SYNC_ERR
TP2
LOL
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Evaluates: MAX3953
RATESET C9 0.047F VCC VCC R22 OPEN R21 OPEN VCC R20 OPEN R19 OPEN R18 OPEN J40 J39 SMB SMB J38 J37 SMB SMB J34 J33 SMB SMB J32 J31 SMB SMB J36 J35 SMB SMB
FIL
VCC
GND
GND
VCC
PD01-
PD02-
PD03-
PD00+
PD01+
PD02+
PD03+
PD04-
C2 0.1F GND GND CLKSEL TP1 CLKSEL SYNC_ERR PDO5PDO5+ PDO6PDO6+ 46 45 44 PDO743 PDO7+ VCC PDO8PDO8+ PDO9PDO9+ PDO10PDO10+ GND PD014+ PD014VCC PD013+ PD013PD012+ PD012PD011+ PD011GND 42 41 40 39 38 37 36 35 R11 OPEN J19 SMB R12 OPEN R13 OPEN J23 SMB J22 SMB R14 OPEN J25 SMB VCC J24 SMB R15 OPEN J27 SMB J26 SMB 47 R16 OPEN J29 SMB J28 SMB 48 49 J30 SMB SYNC_ERR 50 2 REFCLK+ REFCLKGND GND GND REFSET C4 0.1F 3 4 5 6 7 R1 100
MAX3953 Evaluation Kit
GND
LOS_IN
LOL
PCLKO+
PCLKO-
PD015+
6 VCC 18 19 20 21 22 R5 OPEN 23
5
PD015-
Figure 2. MAX3953 EV Kit Schematic
68 RATESET 1 51 PDO0PD04+ GND 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 REFSET
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U1
C6 0.1F VCC VCC 9 C10 0.1F J4 SMB SDIVCC VCC VCC GND VCC VCC GND VCC VCC SYNC_ERR VCC 14 VCC VCC VCC VCC 17 16 15 13 12 11 10 SDI+ 8
J1 SMB
J2 SMB
MAX3953
J3 SMB
20
JU2
19
18
17
CLKSEL
16
15
14
13
J20 SMB
J21 SMB
REFSET
12
11
10
9
8
7
RATESET
LOS_IN LOS_IN VCC L1 50nH VCC C1 2.2F C3 0.01F C5 0.01F C7 0.01F LOL TP2 C13 0.01F
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24 R6 OPEN J9 J10 SMB SMB 25 26 R7 OPEN J11 J12 SMB SMB 27 28 29 R8 OPEN VCC J13 J14 SMB SMB 30 31 R9 OPEN J15 J16 SMB SMB 32 33 R10 OPEN J17 J18 SMB SMB 34 J7 J8 SMB SMB C15 0.01F C16 0.1F
4
3
2
1
J41
VCC
J42
C8 33F
GND
MAX3953 Evaluation Kit Evaluates: MAX3953
1.0"
Figure 3. MAX3953 EV Kit Component Placement Guide--Component Side
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MAX3953 Evaluation Kit Evaluates: MAX3953
1.0"
1.0"
Figure 4. MAX3953 EV Kit PC Board Layout--Component Side
Figure 5. MAX3953 EV Kit PC Board Layout--Ground Plane
1.0"
1.0"
Figure 6. MAX3953 EV Kit PC Board Layout--Power Plane
Figure 7. MAX3953 EV Kit PC Board Layout--Solder Side
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
6 _____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2002 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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